Technical Field
Embodiments described herein generally relate to processors. In particular, embodiments described herein generally relate to processors to perform instructions to operate on packed data.
Background Information
Many processors have Single instruction. Multiple Data (SIMD) architectures. In SIMD architectures, multiple data elements may be packed within one register or memory location as packed data or vector data. In packed data, the bits of the register or other storage location may be logically divided into a sequence of data elements. For example, a 128-bit wide packed data register may have two 64-bit wide data elements, four 32-bit data elements, eight 16-bit data elements, etc. Each of the data elements may represent a separate individual piece of data (e.g., a pixel color, etc.), which may be operated upon separately and/or independently of the others.